mirror of
https://github.com/N64Recomp/N64Recomp.git
synced 2026-04-28 21:12:24 +00:00
Initial implementation of binary operation table
This commit is contained in:
Mr-Wiseguy
parent
f8d439aeee
commit
7268649c44
1 changed files with 365 additions and 120 deletions
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@ -1,6 +1,8 @@
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#include <vector>
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#include <set>
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#include <unordered_set>
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#include <unordered_map>
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#include <cassert>
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#include "rabbitizer.hpp"
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#include "fmt/format.h"
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@ -18,6 +20,344 @@ std::string_view ctx_gpr_prefix(int reg) {
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return "";
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}
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enum class UnaryOpType {
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None,
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ToS32,
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ToU32,
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ToS64,
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ToU64,
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NegateS32,
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NegateS64,
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Lui,
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Mask5, // Mask to 5 bits
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Mask6, // Mask to 5 bits
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};
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enum class BinaryOpType {
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// Addition/subtraction
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Add32,
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Sub32,
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Add64,
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Sub64,
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// Bitwise
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And64,
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Or64,
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Nor64,
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Xor64,
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Sll32,
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Sll64,
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Srl32,
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Srl64,
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Sra32,
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Sra64,
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Less,
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// Loads
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LD,
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LW,
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LWU,
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LH,
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LHU,
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LB,
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LBU,
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LDL,
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LDR,
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LWL,
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LWR,
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COUNT,
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};
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enum class Operand {
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Rd, // GPR
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Rs, // GPR
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Rt, // GPR
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Fd, // FPR
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Fs, // FPR
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Ft, // FPR
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ImmU16, // 16-bit immediate, unsigned
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ImmS16, // 16-bit immediate, signed
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Sa, // Shift amount
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Sa32, // Shift amount plus 32
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Base = Rs, // Alias for Rs for loads
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};
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struct UnaryOp {
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UnaryOpType operation;
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Operand output;
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Operand input;
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};
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struct BinaryOp {
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// The type of binary operation this represents.
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BinaryOpType type;
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// Operation to apply to each operand before applying the binary operation to them.
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UnaryOpType operand_operations[2];
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// The output operand.
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Operand output;
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// The source of the input operands.
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Operand operands[2];
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};
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const std::unordered_map<InstrId, UnaryOp> unary_ops {
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{ InstrId::cpu_lui, { UnaryOpType::Lui, Operand::Rt, Operand::ImmU16 } },
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};
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const std::unordered_map<InstrId, BinaryOp> binary_ops {
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// Addition/subtraction
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{ InstrId::cpu_addu, { BinaryOpType::Add32, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_add, { BinaryOpType::Add32, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_negu, { BinaryOpType::Sub32, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} }, // pseudo op for subu
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{ InstrId::cpu_subu, { BinaryOpType::Sub32, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_sub, { BinaryOpType::Sub32, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_daddu, { BinaryOpType::Add64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_dadd, { BinaryOpType::Add64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_dsubu, { BinaryOpType::Sub64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_dsub, { BinaryOpType::Sub64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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// Addition/subtraction (immediate)
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{ InstrId::cpu_addi, { BinaryOpType::Add32, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::Rs, Operand::ImmS16 }} },
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{ InstrId::cpu_addiu, { BinaryOpType::Add32, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::Rs, Operand::ImmS16 }} },
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{ InstrId::cpu_daddi, { BinaryOpType::Add64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::Rs, Operand::ImmS16 }} },
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{ InstrId::cpu_daddiu, { BinaryOpType::Add64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::Rs, Operand::ImmS16 }} },
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// Bitwise
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{ InstrId::cpu_and, { BinaryOpType::And64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_or, { BinaryOpType::Or64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_nor, { BinaryOpType::Nor64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_xor, { BinaryOpType::Xor64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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// Bitwise (immediate)
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{ InstrId::cpu_andi, { BinaryOpType::And64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::Rs, Operand::ImmU16 }} },
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{ InstrId::cpu_ori, { BinaryOpType::Or64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::Rs, Operand::ImmU16 }} },
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{ InstrId::cpu_xori, { BinaryOpType::Xor64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::Rs, Operand::ImmU16 }} },
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// Shifts
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/* BUG Should mask after (change op to Sll32 and input op to ToU32) */
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{ InstrId::cpu_sllv, { BinaryOpType::Sll64, { UnaryOpType::ToS32, UnaryOpType::Mask5 }, Operand::Rd, { Operand::Rt, Operand::Rs }} },
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{ InstrId::cpu_dsllv, { BinaryOpType::Sll64, { UnaryOpType::None, UnaryOpType::Mask6 }, Operand::Rd, { Operand::Rt, Operand::Rs }} },
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{ InstrId::cpu_srlv, { BinaryOpType::Srl32, { UnaryOpType::ToU32, UnaryOpType::Mask5 }, Operand::Rd, { Operand::Rt, Operand::Rs }} },
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{ InstrId::cpu_dsrlv, { BinaryOpType::Srl64, { UnaryOpType::ToU64, UnaryOpType::Mask6 }, Operand::Rd, { Operand::Rt, Operand::Rs }} },
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/* BUG Should mask after (change op to Sra32 and input op to ToS64) */
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{ InstrId::cpu_srav, { BinaryOpType::Sra64, { UnaryOpType::ToS32, UnaryOpType::Mask5 }, Operand::Rd, { Operand::Rt, Operand::Rs }} },
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{ InstrId::cpu_dsrav, { BinaryOpType::Sra64, { UnaryOpType::ToS64, UnaryOpType::Mask6 }, Operand::Rd, { Operand::Rt, Operand::Rs }} },
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// Shifts (immediate)
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/* BUG Should mask after (change op to Sll32 and input op to ToU32) */
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{ InstrId::cpu_sll, { BinaryOpType::Sll64, { UnaryOpType::ToS32, UnaryOpType::None }, Operand::Rd, { Operand::Rt, Operand::Sa }} },
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{ InstrId::cpu_dsll, { BinaryOpType::Sll64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rt, Operand::Sa }} },
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{ InstrId::cpu_dsll32, { BinaryOpType::Sll64, { UnaryOpType::None, UnaryOpType::None }, Operand::Rd, { Operand::Rt, Operand::Sa32 }} },
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{ InstrId::cpu_srl, { BinaryOpType::Srl32, { UnaryOpType::ToU32, UnaryOpType::None }, Operand::Rd, { Operand::Rt, Operand::Sa }} },
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{ InstrId::cpu_dsrl, { BinaryOpType::Srl64, { UnaryOpType::ToU64, UnaryOpType::None }, Operand::Rd, { Operand::Rt, Operand::Sa }} },
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{ InstrId::cpu_dsrl32, { BinaryOpType::Srl64, { UnaryOpType::ToU64, UnaryOpType::None }, Operand::Rd, { Operand::Rt, Operand::Sa32 }} },
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/* BUG should cast after (change op to Sra32 and input op to ToS64) */
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{ InstrId::cpu_sra, { BinaryOpType::Sra64, { UnaryOpType::ToS32, UnaryOpType::None }, Operand::Rd, { Operand::Rt, Operand::Sa }} },
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{ InstrId::cpu_dsra, { BinaryOpType::Sra64, { UnaryOpType::ToS64, UnaryOpType::None }, Operand::Rd, { Operand::Rt, Operand::Sa }} },
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{ InstrId::cpu_dsra32, { BinaryOpType::Sra64, { UnaryOpType::ToS64, UnaryOpType::None }, Operand::Rd, { Operand::Rt, Operand::Sa32 }} },
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// Comparisons
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{ InstrId::cpu_slt, { BinaryOpType::Less, { UnaryOpType::ToS64, UnaryOpType::ToS64 }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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{ InstrId::cpu_sltu, { BinaryOpType::Less, { UnaryOpType::ToU64, UnaryOpType::ToU64 }, Operand::Rd, { Operand::Rs, Operand::Rt }} },
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// Comparisons (immediate)
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{ InstrId::cpu_slti, { BinaryOpType::Less, { UnaryOpType::ToS64, UnaryOpType::None }, Operand::Rt, { Operand::Rs, Operand::ImmS16 }} },
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{ InstrId::cpu_sltiu, { BinaryOpType::Less, { UnaryOpType::ToU64, UnaryOpType::None }, Operand::Rt, { Operand::Rs, Operand::ImmS16 }} },
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// Loads
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{ InstrId::cpu_ld, { BinaryOpType::LD, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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{ InstrId::cpu_lw, { BinaryOpType::LW, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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{ InstrId::cpu_lwu, { BinaryOpType::LWU, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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{ InstrId::cpu_lh, { BinaryOpType::LH, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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{ InstrId::cpu_lhu, { BinaryOpType::LHU, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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{ InstrId::cpu_lb, { BinaryOpType::LB, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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{ InstrId::cpu_lbu, { BinaryOpType::LBU, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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{ InstrId::cpu_ldl, { BinaryOpType::LDL, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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{ InstrId::cpu_ldr, { BinaryOpType::LDR, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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{ InstrId::cpu_lwl, { BinaryOpType::LWL, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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{ InstrId::cpu_lwr, { BinaryOpType::LWR, { UnaryOpType::None, UnaryOpType::None }, Operand::Rt, { Operand::ImmS16, Operand::Base }} },
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};
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struct InstructionContext {
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int rd;
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int rs;
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int rt;
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int sa;
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int fd;
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int fs;
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int ft;
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int cop1_cs;
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uint16_t imm16;
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};
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class CGenerator {
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public:
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CGenerator() = default;
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void process_binary_op(std::ostream& output_file, const BinaryOp& op, const InstructionContext& ctx);
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private:
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void get_operand_string(Operand operand, UnaryOpType operation, const InstructionContext& context, std::string& operand_string);
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void get_notation(BinaryOpType op_type, std::string& func_string, std::string& infix_string);
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};
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struct BinaryOpFields { std::string func_string; std::string infix_string; };
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std::vector<BinaryOpFields> c_op_fields = []() {
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std::vector<BinaryOpFields> ret{};
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ret.resize(static_cast<size_t>(BinaryOpType::COUNT));
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std::vector<char> ops_setup{};
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ops_setup.resize(static_cast<size_t>(BinaryOpType::COUNT));
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auto setup_op = [&ret, &ops_setup](BinaryOpType op_type, const std::string& func_string, const std::string& infix_string) {
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size_t index = static_cast<size_t>(op_type);
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// Prevent setting up an operation twice.
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assert(ops_setup[index] == false, "Operation already setup!");
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ops_setup[index] = true;
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ret[index] = { func_string, infix_string };
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};
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setup_op(BinaryOpType::Add32, "ADD32", "");
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setup_op(BinaryOpType::Sub32, "SUB32", "");
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setup_op(BinaryOpType::Add64, "", "+");
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setup_op(BinaryOpType::Sub64, "", "-");
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setup_op(BinaryOpType::And64, "", "&");
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setup_op(BinaryOpType::Or64, "", "|");
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setup_op(BinaryOpType::Nor64, "~", "|");
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setup_op(BinaryOpType::Xor64, "", "^");
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setup_op(BinaryOpType::Sll32, "S32", "<<");
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setup_op(BinaryOpType::Sll64, "", "<<");
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setup_op(BinaryOpType::Srl32, "S32", ">>");
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setup_op(BinaryOpType::Srl64, "", ">>");
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setup_op(BinaryOpType::Sra32, "S32", ">>"); // Arithmetic aspect will be taken care of by unary op for first operand.
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setup_op(BinaryOpType::Sra64, "", ">>"); // Arithmetic aspect will be taken care of by unary op for first operand.
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setup_op(BinaryOpType::Less, "", "<");
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setup_op(BinaryOpType::LD, "LD", "");
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setup_op(BinaryOpType::LW, "MEM_W", "");
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setup_op(BinaryOpType::LWU, "MEM_WU", "");
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setup_op(BinaryOpType::LH, "MEM_H", "");
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setup_op(BinaryOpType::LHU, "MEM_HU", "");
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setup_op(BinaryOpType::LB, "MEM_B", "");
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setup_op(BinaryOpType::LBU, "MEM_BU", "");
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setup_op(BinaryOpType::LDL, "do_ldl", "");
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setup_op(BinaryOpType::LDR, "do_ldr", "");
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setup_op(BinaryOpType::LWL, "do_lwl", "");
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setup_op(BinaryOpType::LWR, "do_lwr", "");
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// Ensure every operation has been setup.
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for (char is_set : ops_setup) {
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assert(is_set, "Operation has not been setup!");
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}
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return ret;
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}();
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std::string gpr_to_string(int gpr_index) {
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if (gpr_index == 0) {
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return "0";
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}
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return fmt::format("ctx->r{}", gpr_index);
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}
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void CGenerator::get_operand_string(Operand operand, UnaryOpType operation, const InstructionContext& context, std::string& operand_string) {
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switch (operand) {
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case Operand::Rd:
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operand_string = gpr_to_string(context.rd);
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break;
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case Operand::Rs:
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operand_string = gpr_to_string(context.rs);
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break;
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case Operand::Rt:
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operand_string = gpr_to_string(context.rt);
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break;
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case Operand::Fd:
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assert(false);
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break;
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case Operand::Fs:
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assert(false);
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break;
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case Operand::Ft:
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assert(false);
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break;
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case Operand::ImmU16:
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operand_string = fmt::format("{:#X}", context.imm16);
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break;
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case Operand::ImmS16:
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operand_string = fmt::format("{:#X}", (int16_t)context.imm16);
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break;
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case Operand::Sa:
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operand_string = std::to_string(context.sa);
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break;
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case Operand::Sa32:
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operand_string = fmt::format("({} + 32)", context.sa);
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break;
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}
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switch (operation) {
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case UnaryOpType::None:
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break;
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case UnaryOpType::ToS32:
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operand_string = "S32(" + operand_string + ")";
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break;
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case UnaryOpType::ToU32:
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operand_string = "U32(" + operand_string + ")";
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break;
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case UnaryOpType::ToS64:
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operand_string = "SIGNED(" + operand_string + ")";
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break;
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case UnaryOpType::ToU64:
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// Nothing to do here, they're already U64
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break;
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case UnaryOpType::NegateS32:
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assert(false);
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break;
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case UnaryOpType::NegateS64:
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assert(false);
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break;
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case UnaryOpType::Lui:
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assert(false);
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// operand_string = "S32(" + operand_string + ")";
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break;
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case UnaryOpType::Mask5:
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operand_string = "(" + operand_string + " & 31)";
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break;
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case UnaryOpType::Mask6:
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operand_string = "(" + operand_string + " & 63)";
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break;
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}
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}
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void CGenerator::get_notation(BinaryOpType op_type, std::string& func_string, std::string& infix_string) {
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func_string = c_op_fields[static_cast<size_t>(op_type)].func_string;
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infix_string = c_op_fields[static_cast<size_t>(op_type)].infix_string;
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}
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void CGenerator::process_binary_op(std::ostream& output_file, const BinaryOp& op, const InstructionContext& ctx) {
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// Thread local variables to prevent allocations when possible.
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// TODO these thread locals probably don't actually help right now, so figure out a better way to prevent allocations.
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thread_local std::string output{};
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thread_local std::string input_a{};
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thread_local std::string input_b{};
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thread_local std::string func_string{};
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thread_local std::string infix_string{};
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bool is_infix;
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get_operand_string(op.output, UnaryOpType::None, ctx, output);
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get_operand_string(op.operands[0], op.operand_operations[0], ctx, input_a);
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get_operand_string(op.operands[1], op.operand_operations[1], ctx, input_b);
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get_notation(op.type, func_string, infix_string);
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// Not strictly necessary, just here to have parity with the old recompiler output.
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if (op.type == BinaryOpType::Less) {
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fmt::print(output_file, "{} = {} {} {} ? 1 : 0;\n", output, input_a, infix_string, input_b);
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}
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// TODO encode these ops to avoid needing special handling.
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||||
else if (op.type == BinaryOpType::LWL || op.type == BinaryOpType::LWR || op.type == BinaryOpType::LDL || op.type == BinaryOpType::LDR) {
|
||||
fmt::print(output_file, "{} = {}(rdram, {}, {}, {});\n", output, func_string, output, input_a, input_b);
|
||||
}
|
||||
else if (!func_string.empty() && !infix_string.empty()) {
|
||||
fmt::print(output_file, "{} = {}({} {} {});\n", output, func_string, input_a, infix_string, input_b);
|
||||
}
|
||||
else if (!func_string.empty()) {
|
||||
fmt::print(output_file, "{} = {}({}, {});\n", output, func_string, input_a, input_b);
|
||||
}
|
||||
else if (!infix_string.empty()) {
|
||||
fmt::print(output_file, "{} = {} {} {};\n", output, input_a, infix_string, input_b);
|
||||
}
|
||||
else {
|
||||
assert(false, "Binary operation must have either a function or infix!");
|
||||
}
|
||||
}
|
||||
|
||||
enum class JalResolutionResult {
|
||||
NoMatch,
|
||||
Match,
|
||||
|
|
@ -376,6 +716,8 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
|
|||
}
|
||||
}
|
||||
|
||||
bool handled = true;
|
||||
|
||||
switch (instr.getUniqueId()) {
|
||||
case InstrId::cpu_nop:
|
||||
fmt::print(output_file, "\n");
|
||||
|
|
@ -425,101 +767,6 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
|
|||
print_line("gpr jr_addend_{:08X} = {}{}", cur_jtbl.jr_vram, ctx_gpr_prefix(cur_jtbl.addend_reg), cur_jtbl.addend_reg);
|
||||
}
|
||||
}
|
||||
print_line("{}{} = ADD32({}{}, {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_daddu:
|
||||
print_line("{}{} = {}{} + {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_negu: // pseudo instruction for subu x, 0, y
|
||||
case InstrId::cpu_sub:
|
||||
case InstrId::cpu_subu:
|
||||
print_line("{}{} = SUB32({}{}, {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_addi:
|
||||
case InstrId::cpu_addiu:
|
||||
print_line("{}{} = ADD32({}{}, {})", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, signed_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_daddi:
|
||||
case InstrId::cpu_daddiu:
|
||||
print_line("{}{} = {}{} + {}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, signed_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_and:
|
||||
print_line("{}{} = {}{} & {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_andi:
|
||||
print_line("{}{} = {}{} & {}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, unsigned_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_or:
|
||||
print_line("{}{} = {}{} | {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_ori:
|
||||
print_line("{}{} = {}{} | {}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, unsigned_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_nor:
|
||||
print_line("{}{} = ~({}{} | {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_xor:
|
||||
print_line("{}{} = {}{} ^ {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_xori:
|
||||
print_line("{}{} = {}{} ^ {}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, unsigned_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_sll:
|
||||
print_line("{}{} = S32({}{}) << {}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_dsll:
|
||||
print_line("{}{} = {}{} << {}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_dsll32:
|
||||
print_line("{}{} = ((gpr)({}{})) << ({} + 32)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_sllv:
|
||||
print_line("{}{} = S32({}{}) << ({}{} & 31)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
|
||||
break;
|
||||
case InstrId::cpu_dsllv:
|
||||
print_line("{}{} = {}{} << ({}{} & 63)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
|
||||
break;
|
||||
case InstrId::cpu_sra:
|
||||
print_line("{}{} = S32({}{}) >> {}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_dsra:
|
||||
print_line("{}{} = SIGNED({}{}) >> {}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_dsra32:
|
||||
print_line("{}{} = SIGNED({}{}) >> ({} + 32)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_srav:
|
||||
print_line("{}{} = S32({}{}) >> ({}{} & 31)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
|
||||
break;
|
||||
case InstrId::cpu_dsrav:
|
||||
print_line("{}{} = SIGNED({}{}) >> ({}{} & 63)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
|
||||
break;
|
||||
case InstrId::cpu_srl:
|
||||
print_line("{}{} = S32(U32({}{}) >> {})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_dsrl:
|
||||
print_line("{}{} = {}{} >> {}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_dsrl32:
|
||||
print_line("{}{} = ((gpr)({}{})) >> ({} + 32)", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
break;
|
||||
case InstrId::cpu_srlv:
|
||||
print_line("{}{} = S32(U32({}{}) >> ({}{} & 31))", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
|
||||
break;
|
||||
case InstrId::cpu_dsrlv:
|
||||
print_line("{}{} = {}{} >> ({}{} & 63))", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs);
|
||||
break;
|
||||
case InstrId::cpu_slt:
|
||||
print_line("{}{} = SIGNED({}{}) < SIGNED({}{}) ? 1 : 0", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_slti:
|
||||
print_line("{}{} = SIGNED({}{}) < {} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, signed_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_sltu:
|
||||
print_line("{}{} = {}{} < {}{} ? 1 : 0", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_sltiu:
|
||||
print_line("{}{} = {}{} < {} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, signed_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_mult:
|
||||
print_line("result = S64(S32({}{})) * S64(S32({}{})); lo = S32(result >> 0); hi = S32(result >> 32)", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
|
|
@ -558,25 +805,6 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
|
|||
case InstrId::cpu_mthi:
|
||||
print_line("hi = {}{}", ctx_gpr_prefix(rs), rs);
|
||||
break;
|
||||
// Loads
|
||||
case InstrId::cpu_ld:
|
||||
print_line("{}{} = LD({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lw:
|
||||
print_line("{}{} = MEM_W({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lh:
|
||||
print_line("{}{} = MEM_H({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lb:
|
||||
print_line("{}{} = MEM_B({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lhu:
|
||||
print_line("{}{} = MEM_HU({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lbu:
|
||||
print_line("{}{} = MEM_BU({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
// Stores
|
||||
case InstrId::cpu_sd:
|
||||
print_line("SD({}{}, {}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
|
|
@ -604,12 +832,6 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
|
|||
// LWR x + 1 -> 00000000 012389AB
|
||||
// LWR x + 2 -> 00000000 0189ABCD
|
||||
// LWR x + 3 -> FFFFFFFF 89ABCDEF
|
||||
case InstrId::cpu_lwl:
|
||||
print_line("{}{} = do_lwl(rdram, {}{}, {}, {}{})", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lwr:
|
||||
print_line("{}{} = do_lwr(rdram, {}{}, {}, {}{})", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
// Unaligned stores
|
||||
// examples:
|
||||
// reg = 11111111 01234567
|
||||
|
|
@ -1221,6 +1443,29 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::C
|
|||
print_line("ctx->f{}.u32l = S32(floor(ctx->f{}.d))", fd, fs);
|
||||
break;
|
||||
default:
|
||||
handled = false;
|
||||
break;
|
||||
}
|
||||
|
||||
auto find_it = binary_ops.find(instr.getUniqueId());
|
||||
if (find_it != binary_ops.end()) {
|
||||
CGenerator generator{};
|
||||
InstructionContext instruction_context{};
|
||||
instruction_context.rd = rd;
|
||||
instruction_context.rs = rs;
|
||||
instruction_context.rt = rt;
|
||||
instruction_context.sa = sa;
|
||||
instruction_context.fd = fd;
|
||||
instruction_context.fs = fs;
|
||||
instruction_context.ft = ft;
|
||||
instruction_context.cop1_cs = cop1_cs;
|
||||
instruction_context.imm16 = imm;
|
||||
print_indent();
|
||||
generator.process_binary_op(output_file, find_it->second, instruction_context);
|
||||
handled = true;
|
||||
}
|
||||
|
||||
if (!handled) {
|
||||
fmt::print(stderr, "Unhandled instruction: {}\n", instr.getOpcodeName());
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue