mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2026-02-04 04:35:57 +00:00
Merge 180084ca55 into 5a945705de
This commit is contained in:
Mystixor
GitHub
commit
606fc10e20
6 changed files with 564 additions and 155 deletions
3
.gitmodules
vendored
3
.gitmodules
vendored
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@ -13,3 +13,6 @@
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[submodule "thirdparty/tiny-AES-c"]
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path = thirdparty/tiny-AES-c
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url = https://github.com/kokke/tiny-AES-c.git
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[submodule "thirdparty/simde"]
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path = thirdparty/simde
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url = https://github.com/simd-everywhere/simde-no-tests.git
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@ -16,4 +16,4 @@
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#include <xbox.h>
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#include <xxhash.h>
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#include <fmt/core.h>
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#include <xmmintrin.h>
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#include <x86/sse.h>
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File diff suppressed because it is too large
Load diff
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@ -17,8 +17,9 @@ target_compile_definitions(XenonUtils
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)
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target_include_directories(XenonUtils
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PUBLIC
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PUBLIC
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.
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"${THIRDPARTY_ROOT}/simde"
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PRIVATE
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"${THIRDPARTY_ROOT}/libmspack/libmspack/mspack"
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"${THIRDPARTY_ROOT}/tiny-AES-c"
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@ -12,13 +12,13 @@
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#include <cstdlib>
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#include <cstring>
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#include <x86intrin.h>
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#include <x86/avx.h>
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#include <x86/sse.h>
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#include <x86/sse4.1.h>
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#ifdef _WIN32
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#include <intrin.h>
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#else
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#include <xmmintrin.h>
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#include <smmintrin.h>
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// SSE3 constants are missing from simde
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#ifndef _MM_DENORMALS_ZERO_MASK
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#define _MM_DENORMALS_ZERO_MASK 0x0040
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#endif
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#define PPC_JOIN(x, y) x##y
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@ -172,18 +172,18 @@ struct PPCCRRegister
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eq = !un && (left == right);
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}
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inline void setFromMask(__m128 mask, int imm) noexcept
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inline void setFromMask(simde__m128 mask, int imm) noexcept
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{
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int m = _mm_movemask_ps(mask);
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int m = simde_mm_movemask_ps(mask);
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lt = m == imm; // all equal
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gt = 0;
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eq = m == 0; // none equal
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so = 0;
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}
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inline void setFromMask(__m128i mask, int imm) noexcept
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inline void setFromMask(simde__m128i mask, int imm) noexcept
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{
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int m = _mm_movemask_epi8(mask);
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int m = simde_mm_movemask_epi8(mask);
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lt = m == imm; // all equal
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gt = 0;
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eq = m == 0; // none equal
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@ -215,34 +215,71 @@ struct PPCFPSCRRegister
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{
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uint32_t csr;
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static constexpr size_t GuestToHost[] = { _MM_ROUND_NEAREST, _MM_ROUND_TOWARD_ZERO, _MM_ROUND_UP, _MM_ROUND_DOWN };
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static constexpr size_t HostToGuest[] = { PPC_ROUND_NEAREST, PPC_ROUND_DOWN, PPC_ROUND_UP, PPC_ROUND_TOWARD_ZERO };
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// simde does not handle denormal flags, so we need to implement per-arch.
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#if defined(__x86_64__) || defined(_M_X64)
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static constexpr size_t RoundShift = 13;
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static constexpr size_t RoundMask = SIMDE_MM_ROUND_MASK;
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static constexpr size_t FlushMask = SIMDE_MM_FLUSH_ZERO_MASK | _MM_DENORMALS_ZERO_MASK;
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static constexpr size_t GuestToHost[] = { SIMDE_MM_ROUND_NEAREST, SIMDE_MM_ROUND_TOWARD_ZERO, SIMDE_MM_ROUND_UP, SIMDE_MM_ROUND_DOWN };
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inline uint32_t getcsr() noexcept
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{
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return simde_mm_getcsr();
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}
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inline void setcsr(uint32_t csr) noexcept
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{
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simde_mm_setcsr(csr);
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}
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#elif defined(__aarch64__) || defined(_M_ARM64)
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// RMode
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static constexpr size_t RoundShift = 22;
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static constexpr size_t RoundMask = 3 << RoundShift;
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// FZ and FZ16
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static constexpr size_t FlushMask = (1 << 19) | (1 << 24);
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// Nearest, Zero, -Infinity, -Infinity
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static constexpr size_t GuestToHost[] = { 0 << RoundShift, 3 << RoundShift, 1 << RoundShift, 2 << RoundShift };
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inline uint32_t getcsr() noexcept
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{
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uint64_t csr;
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__asm__ __volatile__("mrs %0, fpcr" : "=r"(csr));
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return csr;
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}
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inline void setcsr(uint32_t csr) noexcept
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{
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__asm__ __volatile__("msr fpcr, %0" : : "r"(csr));
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}
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#else
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# error "Missing implementation for FPSCR."
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#endif
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inline uint32_t loadFromHost() noexcept
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{
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csr = _mm_getcsr();
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return HostToGuest[(csr & _MM_ROUND_MASK) >> 13];
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csr = getcsr();
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return HostToGuest[(csr & RoundMask) >> RoundShift];
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}
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inline void storeFromGuest(uint32_t value) noexcept
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{
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csr &= ~_MM_ROUND_MASK;
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csr &= ~RoundMask;
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csr |= GuestToHost[value & PPC_ROUND_MASK];
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_mm_setcsr(csr);
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setcsr(csr);
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}
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static constexpr size_t FlushMask = _MM_FLUSH_ZERO_MASK | _MM_DENORMALS_ZERO_MASK;
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inline void enableFlushModeUnconditional() noexcept
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{
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csr |= FlushMask;
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_mm_setcsr(csr);
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setcsr(csr);
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}
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inline void disableFlushModeUnconditional() noexcept
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{
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csr &= ~FlushMask;
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_mm_setcsr(csr);
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setcsr(csr);
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}
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inline void enableFlushMode() noexcept
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@ -250,7 +287,7 @@ struct PPCFPSCRRegister
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if ((csr & FlushMask) != FlushMask) [[unlikely]]
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{
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csr |= FlushMask;
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_mm_setcsr(csr);
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setcsr(csr);
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}
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}
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@ -259,7 +296,7 @@ struct PPCFPSCRRegister
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if ((csr & FlushMask) != 0) [[unlikely]]
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{
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csr &= ~FlushMask;
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_mm_setcsr(csr);
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setcsr(csr);
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}
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}
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};
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@ -587,68 +624,93 @@ inline uint8_t VectorShiftTableR[] =
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0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
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};
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inline __m128i _mm_adds_epu32(__m128i a, __m128i b)
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inline simde__m128i simde_mm_adds_epu32(simde__m128i a, simde__m128i b)
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{
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return _mm_add_epi32(a, _mm_min_epu32(_mm_xor_si128(a, _mm_cmpeq_epi32(a, a)), b));
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return simde_mm_add_epi32(a, simde_mm_min_epu32(simde_mm_xor_si128(a, simde_mm_cmpeq_epi32(a, a)), b));
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}
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inline __m128i _mm_avg_epi8(__m128i a, __m128i b)
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inline simde__m128i simde_mm_avg_epi8(simde__m128i a, simde__m128i b)
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{
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__m128i c = _mm_set1_epi8(char(128));
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return _mm_xor_si128(c, _mm_avg_epu8(_mm_xor_si128(c, a), _mm_xor_si128(c, b)));
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simde__m128i c = simde_mm_set1_epi8(char(128));
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return simde_mm_xor_si128(c, simde_mm_avg_epu8(simde_mm_xor_si128(c, a), simde_mm_xor_si128(c, b)));
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}
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inline __m128i _mm_avg_epi16(__m128i a, __m128i b)
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inline simde__m128i simde_mm_avg_epi16(simde__m128i a, simde__m128i b)
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{
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__m128i c = _mm_set1_epi16(short(32768));
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return _mm_xor_si128(c, _mm_avg_epu16(_mm_xor_si128(c, a), _mm_xor_si128(c, b)));
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simde__m128i c = simde_mm_set1_epi16(short(32768));
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return simde_mm_xor_si128(c, simde_mm_avg_epu16(simde_mm_xor_si128(c, a), simde_mm_xor_si128(c, b)));
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}
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inline __m128 _mm_cvtepu32_ps_(__m128i src1)
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inline simde__m128 simde_mm_cvtepu32_ps_(simde__m128i src1)
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{
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__m128i xmm1 = _mm_add_epi32(src1, _mm_set1_epi32(127));
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__m128i xmm0 = _mm_slli_epi32(src1, 31 - 8);
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xmm0 = _mm_srli_epi32(xmm0, 31);
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xmm0 = _mm_add_epi32(xmm0, xmm1);
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xmm0 = _mm_srai_epi32(xmm0, 8);
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xmm0 = _mm_add_epi32(xmm0, _mm_set1_epi32(0x4F800000));
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__m128 xmm2 = _mm_cvtepi32_ps(src1);
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return _mm_blendv_ps(xmm2, _mm_castsi128_ps(xmm0), _mm_castsi128_ps(src1));
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simde__m128i xmm1 = simde_mm_add_epi32(src1, simde_mm_set1_epi32(127));
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simde__m128i xmm0 = simde_mm_slli_epi32(src1, 31 - 8);
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xmm0 = simde_mm_srli_epi32(xmm0, 31);
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xmm0 = simde_mm_add_epi32(xmm0, xmm1);
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xmm0 = simde_mm_srai_epi32(xmm0, 8);
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xmm0 = simde_mm_add_epi32(xmm0, simde_mm_set1_epi32(0x4F800000));
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simde__m128 xmm2 = simde_mm_cvtepi32_ps(src1);
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return simde_mm_blendv_ps(xmm2, simde_mm_castsi128_ps(xmm0), simde_mm_castsi128_ps(src1));
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}
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inline __m128i _mm_perm_epi8_(__m128i a, __m128i b, __m128i c)
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inline simde__m128i simde_mm_perm_epi8_(simde__m128i a, simde__m128i b, simde__m128i c)
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{
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__m128i d = _mm_set1_epi8(0xF);
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__m128i e = _mm_sub_epi8(d, _mm_and_si128(c, d));
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return _mm_blendv_epi8(_mm_shuffle_epi8(a, e), _mm_shuffle_epi8(b, e), _mm_slli_epi32(c, 3));
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simde__m128i d = simde_mm_set1_epi8(0xF);
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simde__m128i e = simde_mm_sub_epi8(d, simde_mm_and_si128(c, d));
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return simde_mm_blendv_epi8(simde_mm_shuffle_epi8(a, e), simde_mm_shuffle_epi8(b, e), simde_mm_slli_epi32(c, 3));
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}
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inline __m128i _mm_cmpgt_epu8(__m128i a, __m128i b)
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inline simde__m128i simde_mm_cmpgt_epu8(simde__m128i a, simde__m128i b)
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{
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__m128i c = _mm_set1_epi8(char(128));
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return _mm_cmpgt_epi8(_mm_xor_si128(a, c), _mm_xor_si128(b, c));
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simde__m128i c = simde_mm_set1_epi8(char(128));
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return simde_mm_cmpgt_epi8(simde_mm_xor_si128(a, c), simde_mm_xor_si128(b, c));
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}
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inline __m128i _mm_cmpgt_epu16(__m128i a, __m128i b)
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inline simde__m128i simde_mm_cmpgt_epu16(simde__m128i a, simde__m128i b)
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{
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__m128i c = _mm_set1_epi16(short(32768));
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return _mm_cmpgt_epi16(_mm_xor_si128(a, c), _mm_xor_si128(b, c));
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simde__m128i c = simde_mm_set1_epi16(short(32768));
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return simde_mm_cmpgt_epi16(simde_mm_xor_si128(a, c), simde_mm_xor_si128(b, c));
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}
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inline __m128i _mm_vctsxs(__m128 src1)
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inline simde__m128i simde_mm_vctsxs(simde__m128 src1)
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{
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__m128 xmm2 = _mm_cmpunord_ps(src1, src1);
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__m128i xmm0 = _mm_cvttps_epi32(src1);
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__m128i xmm1 = _mm_cmpeq_epi32(xmm0, _mm_set1_epi32(INT_MIN));
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xmm1 = _mm_andnot_si128(_mm_castps_si128(src1), xmm1);
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__m128 dest = _mm_blendv_ps(_mm_castsi128_ps(xmm0), _mm_castsi128_ps(_mm_set1_epi32(INT_MAX)), _mm_castsi128_ps(xmm1));
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return _mm_andnot_si128(_mm_castps_si128(xmm2), _mm_castps_si128(dest));
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simde__m128 xmm2 = simde_mm_cmpunord_ps(src1, src1);
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simde__m128i xmm0 = simde_mm_cvttps_epi32(src1);
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simde__m128i xmm1 = simde_mm_cmpeq_epi32(xmm0, simde_mm_set1_epi32(INT_MIN));
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xmm1 = simde_mm_andnot_si128(simde_mm_castps_si128(src1), xmm1);
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simde__m128 dest = simde_mm_blendv_ps(simde_mm_castsi128_ps(xmm0), simde_mm_castsi128_ps(simde_mm_set1_epi32(INT_MAX)), simde_mm_castsi128_ps(xmm1));
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return simde_mm_andnot_si128(simde_mm_castps_si128(xmm2), simde_mm_castps_si128(dest));
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}
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inline __m128i _mm_vsr(__m128i a, __m128i b)
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inline simde__m128i simde_mm_vsr(simde__m128i a, simde__m128i b)
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{
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b = _mm_srli_epi64(_mm_slli_epi64(b, 61), 61);
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return _mm_castps_si128(_mm_insert_ps(_mm_castsi128_ps(_mm_srl_epi64(a, b)), _mm_castsi128_ps(_mm_srl_epi64(_mm_srli_si128(a, 4), b)), 0x10));
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b = simde_mm_srli_epi64(simde_mm_slli_epi64(b, 61), 61);
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return simde_mm_castps_si128(simde_mm_insert_ps(simde_mm_castsi128_ps(simde_mm_srl_epi64(a, b)), simde_mm_castsi128_ps(simde_mm_srl_epi64(simde_mm_srli_si128(a, 4), b)), 0x10));
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}
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inline simde__m128i simde_mm_vctuxs(simde__m128 src1)
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{
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simde__m128 xmm0 = simde_mm_max_ps(src1, simde_mm_set1_epi32(0));
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simde__m128 xmm1 = simde_mm_cmpge_ps(xmm0, simde_mm_set1_ps((float)0x80000000));
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simde__m128 xmm2 = simde_mm_sub_ps(xmm0, simde_mm_set1_ps((float)0x80000000));
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xmm0 = simde_mm_blendv_ps(xmm0, xmm2, xmm1);
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simde__m128i dest = simde_mm_cvttps_epi32(xmm0);
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xmm0 = simde_mm_cmpeq_epi32(dest, simde_mm_set1_epi32(INT_MIN));
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xmm1 = simde_mm_and_si128(xmm1, simde_mm_set1_epi32(INT_MIN));
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dest = simde_mm_add_epi32(dest, xmm1);
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return simde_mm_or_si128(dest, xmm0);
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}
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#if defined(__aarch64__) || defined(_M_ARM64)
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inline uint64_t __rdtsc()
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{
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uint64_t ret;
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asm volatile("mrs %0, cntvct_el0\n\t"
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: "=r"(ret)::"memory");
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return ret;
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}
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#elif !defined(__x86_64__) && !defined(_M_X64)
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# error "Missing implementation for __rdtsc()"
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#endif
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#endif
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1
thirdparty/simde
vendored
Submodule
1
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vendored
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@ -0,0 +1 @@
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Subproject commit a532a12ca9bbdc5e6547eb602e6256b71a5377d4
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Add table
Reference in a new issue