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Implement additional instructions used by Ridge Racer 6

Browse source 
bns, bnslr, bso, bsolr, eqv, lhbrx, mulhd, vandc, vpkswss, vsel128
This commit is contained in:
Robert B. Langer 2026-01-28 17:26:46 -05:00
parent ddd128bcca
commit 8f31dbe329
1 changed files with 37 additions and 0 deletions
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37
XenonRecomp/recompiler.cpp
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@ -737,6 +737,22 @@ bool Recompiler::Recompile(
case PPC_INST_BNELR:
println("\tif (!{}.eq) return;", cr(insn.operands[0]));
break;
case PPC_INST_BNS:
printConditionalBranch(true, "so");
break;
case PPC_INST_BNSLR:
println("\tif (!{}.so) return;", cr(insn.operands[0]));
break;
case PPC_INST_BSO:
printConditionalBranch(false, "so");
break;
case PPC_INST_BSOLR:
println("\tif ({}.so) return;", cr(insn.operands[0]));
break;
case PPC_INST_CCTPL:
// no op
@ -851,6 +867,10 @@ bool Recompiler::Recompile(
case PPC_INST_EIEIO:
// no op
break;
case PPC_INST_EQV:
println("\t{}.u64 = ~({}.u64 ^ {}.u64);", r(insn.operands[0]), r(insn.operands[1]), r(insn.operands[2]));
break;
case PPC_INST_EXTSB:
println("\t{}.s64 = {}.s8;", r(insn.operands[0]), r(insn.operands[1]));
@ -1111,6 +1131,13 @@ bool Recompiler::Recompile(
println("{}.u32));", r(insn.operands[2]));
break;
case PPC_INST_LHBRX:
print("\t{}.u64 = __builtin_bswap16(PPC_LOAD_U16(", r(insn.operands[0]));
if (insn.operands[1] != 0)
print("{}.u32 + ", r(insn.operands[1]));
println("{}.u32));", r(insn.operands[2]));
break;
case PPC_INST_LHZ:
print("\t{}.u64 = PPC_LOAD_U16(", r(insn.operands[0]));
if (insn.operands[2] != 0)
@ -1300,6 +1327,10 @@ bool Recompiler::Recompile(
println("\t{}.ov = ({}.u64 & 0x40000000) != 0;", xer(), r(insn.operands[0]));
println("\t{}.ca = ({}.u64 & 0x20000000) != 0;", xer(), r(insn.operands[0]));
break;
case PPC_INST_MULHD:
println("\t{}.u64 = uint64_t((__int128_t({}.s64) * __int128_t({}.s64)) >> 64);", r(insn.operands[0]), r(insn.operands[1]), r(insn.operands[2]));
break;
case PPC_INST_MULHW:
println("\t{}.s64 = (int64_t({}.s32) * int64_t({}.s32)) >> 32;", r(insn.operands[0]), r(insn.operands[1]), r(insn.operands[2]));
@ -1769,6 +1800,7 @@ bool Recompiler::Recompile(
println("\tsimde_mm_store_si128((simde__m128i*){}.u8, simde_mm_and_si128(simde_mm_load_si128((simde__m128i*){}.u8), simde_mm_load_si128((simde__m128i*){}.u8)));", v(insn.operands[0]), v(insn.operands[1]), v(insn.operands[2]));
break;
case PPC_INST_VANDC:
case PPC_INST_VANDC128:
println("\tsimde_mm_store_si128((simde__m128i*){}.u8, simde_mm_andnot_si128(simde_mm_load_si128((simde__m128i*){}.u8), simde_mm_load_si128((simde__m128i*){}.u8)));", v(insn.operands[0]), v(insn.operands[2]), v(insn.operands[1]));
break;
@ -2047,6 +2079,10 @@ bool Recompiler::Recompile(
println("\tsimde_mm_store_si128((simde__m128i*){}.u8, simde_mm_packus_epi16(simde_mm_load_si128((simde__m128i*){}.s16), simde_mm_load_si128((simde__m128i*){}.s16)));", v(insn.operands[0]), v(insn.operands[2]), v(insn.operands[1]));
break;
case PPC_INST_VPKSWSS:
println("\tsimde_mm_store_si128((simde__m128i*){}.u8, simde_mm_packs_epi32(simde_mm_load_si128((simde__m128i*){}.s32), simde_mm_load_si128((simde__m128i*){}.s32)));", v(insn.operands[0]), v(insn.operands[2]), v(insn.operands[1]));
break;
case PPC_INST_VREFP:
case PPC_INST_VREFP128:
// TODO: see if we can use rcp safely
@ -2088,6 +2124,7 @@ bool Recompiler::Recompile(
break;
case PPC_INST_VSEL:
case PPC_INST_VSEL128:
println("\tsimde_mm_store_si128((simde__m128i*){}.u8, simde_mm_or_si128(simde_mm_andnot_si128(simde_mm_load_si128((simde__m128i*){}.u8), simde_mm_load_si128((simde__m128i*){}.u8)), simde_mm_and_si128(simde_mm_load_si128((simde__m128i*){}.u8), simde_mm_load_si128((simde__m128i*){}.u8))));", v(insn.operands[0]), v(insn.operands[3]), v(insn.operands[1]), v(insn.operands[3]), v(insn.operands[2]));
break;