mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-10-30 07:11:38 +00:00
Further inaccuracy fixes.
This commit is contained in:
Skyth
parent
0e59052324
commit
fb97a569f9
3 changed files with 95 additions and 34 deletions
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@ -275,8 +275,8 @@ int main(int argc, char* argv[])
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fseek(f, 0, SEEK_SET);
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tempData.resize(fileSize);
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fread(tempData.data(), 1, fileSize, f);
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shouldWrite = XXH3_64bits(tempData.data(), tempData.size()) != XXH3_64bits(out.data(), out.size());
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shouldWrite = !XXH128_isEqual(XXH3_128bits(tempData.data(), tempData.size()), XXH3_128bits(out.data(), out.size()));
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}
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fclose(f);
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}
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@ -364,6 +364,7 @@ int main(int argc, char* argv[])
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if (insn.opcode == nullptr)
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{
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println("\t// {}", insn.op_str);
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std::println("Unable to decode instruction at 0x{:X}", base - 4);
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}
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else
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{
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@ -399,7 +400,13 @@ int main(int argc, char* argv[])
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}
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};
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switch (insn.opcode->id)
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int id = insn.opcode->id;
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// Handling instructions that don't disassemble correctly for some reason here
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if (id == PPC_INST_VUPKHSB128 && insn.operands[2] == 0x60) id = PPC_INST_VUPKHSH128;
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else if (id == PPC_INST_VUPKLSB128 && insn.operands[2] == 0x60) id = PPC_INST_VUPKLSH128;
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switch (id)
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{
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case PPC_INST_ADD:
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println("\tctx.r{}.u64 = ctx.r{}.u64 + ctx.r{}.u64;", insn.operands[0], insn.operands[1], insn.operands[2]);
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@ -758,11 +765,11 @@ int main(int argc, char* argv[])
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break;
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case PPC_INST_FCTIDZ:
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println("\tctx.f{}.s64 = ctx.f{}.f64;", insn.operands[0], insn.operands[1]);
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println("\tctx.f{}.s64 = trunc(ctx.f{}.f64);", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_FCTIWZ:
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println("\tctx.f{}.s32 = ctx.f{}.f64;", insn.operands[0], insn.operands[1]);
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println("\tctx.f{}.s32 = trunc(ctx.f{}.f64);", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_FDIV:
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@ -822,7 +829,7 @@ int main(int argc, char* argv[])
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break;
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case PPC_INST_FRES:
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println("\tctx.f{}.f64 = 1.0 / ctx.f{}.f64;", insn.operands[0], insn.operands[1]);
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println("\tctx.f{}.f64 = 1.0f / float(ctx.f{}.f64);", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_FRSP:
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@ -1260,6 +1267,8 @@ int main(int argc, char* argv[])
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println("\tif (temp.u32 > 0x1F) temp.u32 = 0x1F;");
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println("\tctx.xer.ca = (ctx.r{}.s32 < 0) & (((ctx.r{}.s32 >> temp.u32) << temp.u32) != ctx.r{}.s32);", insn.operands[1], insn.operands[1], insn.operands[1]);
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println("\tctx.r{}.s64 = ctx.r{}.s32 >> {};", insn.operands[0], insn.operands[1], insn.operands[2]);
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if (strchr(insn.opcode->name, '.'))
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println("\tctx.cr0.compare<int32_t>(ctx.r{}.s32, 0, ctx.xer);", insn.operands[0]);
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break;
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case PPC_INST_SRAWI:
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@ -1570,7 +1579,7 @@ int main(int argc, char* argv[])
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break;
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case PPC_INST_VANDC128:
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_andnot_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)));", insn.operands[0], insn.operands[1], insn.operands[2]);
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_andnot_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)));", insn.operands[0], insn.operands[2], insn.operands[1]);
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break;
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case PPC_INST_VAVGSB:
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@ -1587,8 +1596,7 @@ int main(int argc, char* argv[])
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case PPC_INST_VCTSXS:
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case PPC_INST_VCFPSXWS128:
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// TODO: saturate
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println("\t_mm_store_si128((__m128i*)ctx.v{}.s32, _mm_cvttps_epi32(_mm_mul_ps(_mm_load_ps(ctx.v{}.f32), _mm_set1_ps(exp2f({})))));", insn.operands[0], insn.operands[1], insn.operands[2]);
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println("\t_mm_store_si128((__m128i*)ctx.v{}.s32, _mm_vctsxs(_mm_mul_ps(_mm_load_ps(ctx.v{}.f32), _mm_set1_ps(exp2f({})))));", insn.operands[0], insn.operands[1], insn.operands[2]);
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break;
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case PPC_INST_VCFSX:
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@ -1602,6 +1610,7 @@ int main(int argc, char* argv[])
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break;
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case PPC_INST_VCMPBFP128:
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println("\t__debugbreak();");
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break;
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case PPC_INST_VCMPEQFP:
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@ -1717,7 +1726,6 @@ int main(int argc, char* argv[])
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case PPC_INST_VNMSUBFP:
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case PPC_INST_VNMSUBFP128:
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// TODO: wrong argument order
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_fnmadd_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)));", insn.operands[0], insn.operands[1], insn.operands[2], insn.operands[3]);
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break;
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@ -1744,6 +1752,26 @@ int main(int argc, char* argv[])
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}
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case PPC_INST_VPKD3D128:
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// TODO: vectorize somehow?
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// NOTE: handling vector reversal here too
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switch (insn.operands[2])
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{
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case 0: // D3D color
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if (insn.operands[3] != 1 || insn.operands[4] != 3)
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std::println("Unexpected D3D color pack instruction at {:X}", base - 4);
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for (size_t i = 0; i < 4; i++)
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{
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constexpr size_t indices[] = { 3, 0, 1, 2 };
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println("\ttemp.u32 {}= ctx.v{}.u8[{}] << {};", i == 0 ? "" : "|", insn.operands[1], i * 4, indices[i] * 8);
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}
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println("\tctx.v{}.u32[3] = temp.u32;", insn.operands[0]);
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break;
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default:
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println("\t__debugbreak();");
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break;
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}
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break;
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case PPC_INST_VPKSHUS:
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@ -1770,7 +1798,7 @@ int main(int argc, char* argv[])
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case PPC_INST_VRLIMI128:
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{
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constexpr size_t imm[] = { _MM_SHUFFLE(0, 1, 2, 3), _MM_SHUFFLE(1, 2, 3, 0), _MM_SHUFFLE(2, 3, 0, 1), _MM_SHUFFLE(3, 0, 1, 2) };
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constexpr size_t imm[] = { _MM_SHUFFLE(3, 2, 1, 0), _MM_SHUFFLE(2, 1, 0, 3), _MM_SHUFFLE(1, 0, 3, 2), _MM_SHUFFLE(0, 3, 2, 1) };
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_blend_ps(_mm_load_ps(ctx.v{}.f32), _mm_permute_ps(_mm_load_ps(ctx.v{}.f32), {}), {}));", insn.operands[0], insn.operands[0], insn.operands[1], imm[insn.operands[3]], insn.operands[2]);
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break;
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}
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@ -1781,7 +1809,7 @@ int main(int argc, char* argv[])
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break;
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case PPC_INST_VSEL:
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_or_ps(_mm_and_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)), _mm_andnot_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32))));", insn.operands[0], insn.operands[3], insn.operands[1], insn.operands[3], insn.operands[2]);
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println("\t_mm_store_ps(ctx.v{}.f32, _mm_or_ps(_mm_andnot_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32)), _mm_and_ps(_mm_load_ps(ctx.v{}.f32), _mm_load_ps(ctx.v{}.f32))));", insn.operands[0], insn.operands[3], insn.operands[1], insn.operands[3], insn.operands[2]);
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break;
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case PPC_INST_VSLB:
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@ -1805,7 +1833,7 @@ int main(int argc, char* argv[])
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{
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// NOTE: accounting for full vector reversal here
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uint32_t perm = 15 - insn.operands[2];
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_shuffle_epi8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_set1_epi8({})));", insn.operands[0], insn.operands[1], perm);
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_shuffle_epi8(_mm_load_si128((__m128i*)ctx.v{}.u8), _mm_set1_epi8(char(0x{:X}))));", insn.operands[0], insn.operands[1], perm);
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break;
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}
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@ -1814,20 +1842,20 @@ int main(int argc, char* argv[])
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// NOTE: accounting for full vector reversal here
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uint32_t perm = 7 - insn.operands[2];
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perm = (perm * 2) | ((perm * 2 + 1) << 8);
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u16, _mm_shuffle_epi8(_mm_load_si128((__m128i*)ctx.v{}.u16), _mm_set1_epi16(0x{:X})));", insn.operands[0], insn.operands[1], perm);
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u16, _mm_shuffle_epi8(_mm_load_si128((__m128i*)ctx.v{}.u16), _mm_set1_epi16(short(0x{:X}))));", insn.operands[0], insn.operands[1], perm);
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break;
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}
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case PPC_INST_VSPLTISB:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_set1_epi8(0x{:X}));", insn.operands[0], insn.operands[1]);
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u8, _mm_set1_epi8(char(0x{:X})));", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_VSPLTISW:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u32, _mm_set1_epi32(0x{:X}));", insn.operands[0], insn.operands[1]);
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u32, _mm_set1_epi32(int(0x{:X})));", insn.operands[0], insn.operands[1]);
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break;
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case PPC_INST_VSPLTISW128:
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u32, _mm_set1_epi32(0x{:X}));", insn.operands[0], insn.operands[2]);
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println("\t_mm_store_si128((__m128i*)ctx.v{}.u32, _mm_set1_epi32(int(0x{:X})));", insn.operands[0], insn.operands[2]);
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break;
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case PPC_INST_VSPLTW:
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@ -1884,20 +1912,33 @@ int main(int argc, char* argv[])
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case PPC_INST_VUPKD3D128:
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// TODO: vectorize somehow?
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// NOTE: for some reason with binutils 2nd operand is multiplied by 4
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// NOTE: handling vector reversal here too
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switch (insn.operands[2])
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switch (insn.operands[2] >> 2)
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{
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case 4: // 2 shorts
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case 0: // D3D color
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for (size_t i = 0; i < 4; i++)
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{
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constexpr size_t indices[] = { 3, 0, 1, 2 };
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println("\ttemp.f32 = 1.0f;");
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println("\ttemp.u32 |= ctx.v{}.u8[{}];", insn.operands[1], indices[i]);
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println("\tctx.v{}.f32[{}] = temp.f32;", insn.operands[0], i);
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}
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break;
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case 1: // 2 shorts
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for (size_t i = 0; i < 2; i++)
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{
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println("\ttemp.f32 = 3.0f;");
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println("\ttemp.s32 += ctx.v{}.s16[{}];", insn.operands[1], 7 - i); // TODO: not sure about the indexing here
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println("\ttemp.s32 += ctx.v{}.s16[{}];", insn.operands[1], i); // TODO: not sure about the indexing here
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println("\tctx.v{}.f32[{}] = temp.f32;", insn.operands[0], 3 - i);
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}
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println("\tctx.v{}.f32[1] = 0.0f;", insn.operands[0]);
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println("\tctx.v{}.f32[0] = 1.0f;", insn.operands[0]);
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break;
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default:
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println("\t__debugbreak();");
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break;
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}
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break;
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@ -1942,6 +1983,13 @@ int main(int argc, char* argv[])
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std::println("Unrecognized instruction at 0x{:X}: {}", base - 4, insn.opcode->name);
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break;
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}
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if (strchr(insn.opcode->name, '.'))
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{
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int lastLine = out.find_last_of('\n', out.size() - 2);
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if (out.find("ctx.cr", lastLine + 1) == std::string::npos)
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std::println("Instruction at {:X} has RC bit enabled but no comparison was generated", base - 4);
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}
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}
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}
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@ -459,13 +459,13 @@ inline __m128i _mm_adds_epu32(__m128i a, __m128i b)
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inline __m128i _mm_avg_epi8(__m128i a, __m128i b)
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{
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__m128i c = _mm_set1_epi8(char(128));
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return _mm_add_epi8(c, _mm_avg_epu8(_mm_add_epi8(c, a), _mm_add_epi8(c, b)));
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return _mm_xor_si128(c, _mm_avg_epu8(_mm_xor_si128(c, a), _mm_xor_si128(c, b)));
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}
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inline __m128i _mm_avg_epi16(__m128i a, __m128i b)
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{
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__m128i c = _mm_set1_epi16(short(32768));
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return _mm_add_epi16(c, _mm_avg_epu16(_mm_add_epi16(c, a), _mm_add_epi16(c, b)));
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return _mm_xor_si128(c, _mm_avg_epu16(_mm_xor_si128(c, a), _mm_xor_si128(c, b)));
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}
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inline __m128 _mm_cvtepu32_ps_(__m128i v)
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@ -486,13 +486,27 @@ inline __m128i _mm_perm_epi8_(__m128i a, __m128i b, __m128i c)
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inline __m128i _mm_cmpgt_epu8(__m128i a, __m128i b)
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{
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__m128i c = _mm_set1_epi8(0x80);
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__m128i c = _mm_set1_epi8(char(128));
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return _mm_cmpgt_epi8(_mm_xor_si128(a, c), _mm_xor_si128(b, c));
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}
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inline __m128i _mm_cmpgt_epu16(__m128i a, __m128i b)
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{
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__m128i c = _mm_set1_epi16(0x8000);
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__m128i c = _mm_set1_epi16(short(32768));
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return _mm_cmpgt_epi16(_mm_xor_si128(a, c), _mm_xor_si128(b, c));
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}
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inline __m128i _mm_vctsxs(__m128 a)
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{
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__m128i result = _mm_cvttps_epi32(a);
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__m128 max_val = _mm_set1_ps(2147483648.0f);
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__m128 cmp_mask = _mm_cmpgt_ps(a, max_val);
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result = _mm_xor_si128(result, _mm_castps_si128(cmp_mask));
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__m128 ord_mask = _mm_cmpord_ps(a, a);
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result = _mm_and_si128(result, _mm_castps_si128(ord_mask));
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return result;
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}
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17
thirdparty/disasm/ppc-dis.c
vendored
17
thirdparty/disasm/ppc-dis.c
vendored
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@ -843,10 +843,10 @@ const struct powerpc_operand powerpc_operands[] =
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{ 3, 18, NULL, NULL, 0 },
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#define VD3D1 VD3D0 + 1
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{ 2, 16, NULL, NULL, 0 },
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{ 3, 16, NULL, NULL, 0 },
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#define VD3D2 VD3D1 + 1
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{ 2, 6, NULL, NULL, 0 },
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{ 3, 6, NULL, NULL, 0 },
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/* The SIMM field in a VX form instruction. */
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#define SIMM VD3D2 + 1
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@ -1825,10 +1825,10 @@ extract_vperm (unsigned long insn,
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#define VXR_MASK VXR(0x3f, 0x3ff, 1)
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/* An VX128 form instruction. */
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#define VX128(op, xop) (OP(op) | (((unsigned long)(xop)) & 0x7d0))
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#define VX128(op, xop) (OP(op) | (((unsigned long)(xop)) & 0x3d0))
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/* The mask for an VX form instruction. */
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#define VX128_MASK VX(0x3f, 0x7d0)
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#define VX128_MASK VX(0x3f, 0x3d0)
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/* An VX128 form instruction. */
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#define VX128_1(op, xop) (OP(op) | (((unsigned long)(xop)) & 0x7f3))
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@ -2541,11 +2541,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "vminfp128", VX128(6, 704), VX128_MASK, PPCVEC128, { VD128, VA128, VB128 }, PPC_INST_VMINFP128 },
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{ "vmrghw128", VX128(6, 768), VX128_MASK, PPCVEC128, { VD128, VA128, VB128 }, PPC_INST_VMRGHW128 },
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{ "vmrglw128", VX128(6, 832), VX128_MASK, PPCVEC128, { VD128, VA128, VB128 }, PPC_INST_VMRGLW128 },
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{ "vupkhsb128", VX128(6, 896), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKHSB128 },
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{ "vupklsb128", VX128(6, 960), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKLSB128 },
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{ "vupkhsh128", VX128(6, 1952), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKHSH128 },
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{ "vupklsh128", VX128(6, 2016), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKLSH128 },
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{ "vupkhsb128", VX128(6, 896), VX128_MASK, PPCVEC128, { VD128, VB128, VA128 }, PPC_INST_VUPKHSB128 },
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{ "vupklsb128", VX128(6, 960), VX128_MASK, PPCVEC128, { VD128, VB128, VA128 }, PPC_INST_VUPKLSB128 },
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//{ "vupkhsh128", VX128(6, 1952), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKHSH128 },
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//{ "vupklsh128", VX128(6, 2016), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKLSH128 },
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{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVADDW },
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{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM }, PPC_INST_EVADDIW },
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|
|
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Loading…
Add table
Reference in a new issue