mirror of
https://github.com/hedge-dev/XenosRecomp.git
synced 2025-10-30 07:12:17 +00:00
458 lines
No EOL
9.6 KiB
C
458 lines
No EOL
9.6 KiB
C
#pragma once
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enum class ControlFlowOpcode : uint32_t
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{
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Nop = 0,
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Exec = 1,
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ExecEnd = 2,
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CondExec = 3,
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CondExecEnd = 4,
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CondExecPred = 5,
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CondExecPredEnd = 6,
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LoopStart = 7,
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LoopEnd = 8,
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CondCall = 9,
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Return = 10,
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CondJmp = 11,
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Alloc = 12,
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CondExecPredClean = 13,
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CondExecPredCleanEnd = 14,
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MarkVsFetchDone = 15,
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};
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struct ControlFlowExecInstruction
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{
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uint32_t address : 12;
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uint32_t count : 3;
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uint32_t isYield : 1;
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uint32_t sequence : 12;
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uint32_t vertexCacheHigh : 4;
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uint32_t vertexCacheLow : 2;
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uint32_t : 7;
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uint32_t isPredicateClean : 1;
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uint32_t : 1;
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uint32_t absoluteAddressing : 1;
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ControlFlowOpcode opcode : 4;
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};
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struct ControlFlowExecPredInstruction
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{
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uint32_t address : 12;
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uint32_t count : 3;
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uint32_t isYield : 1;
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uint32_t sequence : 12;
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uint32_t vertexCacheHigh : 4;
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uint32_t vertexCacheLow : 2;
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uint32_t : 7;
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uint32_t isPredicateClean : 1;
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uint32_t condition : 1;
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uint32_t absoluteAddressing : 1;
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ControlFlowOpcode opcode : 4;
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};
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struct ControlFlowCondExecInstruction
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{
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uint32_t address : 12;
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uint32_t count : 3;
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uint32_t isYield : 1;
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uint32_t sequence : 12;
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uint32_t vertexCacheHigh : 4;
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uint32_t vertexCacheLow : 2;
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uint32_t boolAddress : 8;
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uint32_t condition : 1;
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uint32_t absoluteAddressing : 1;
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ControlFlowOpcode opcode : 4;
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};
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struct ControlFlowCondExecPredInstruction
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{
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uint32_t address : 12;
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uint32_t count : 3;
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uint32_t isYield : 1;
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uint32_t sequence : 12;
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uint32_t vertexCacheHigh : 4;
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uint32_t vertexCacheLow : 2;
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uint32_t : 7;
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uint32_t isPredicateClean : 1;
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uint32_t condition : 1;
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uint32_t absoluteAddressing : 1;
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ControlFlowOpcode opcode : 4;
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};
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struct ControlFlowLoopStartInstruction
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{
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uint32_t address : 13;
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uint32_t isRepeat : 1;
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uint32_t : 2;
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uint32_t loopId : 5;
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uint32_t : 11;
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uint32_t : 11;
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uint32_t absoluteAddressing : 1;
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ControlFlowOpcode opcode : 4;
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};
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struct ControlFlowLoopEndInstruction
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{
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uint32_t address : 13;
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uint32_t : 3;
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uint32_t loopId : 5;
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uint32_t isPredicatedBreak : 1;
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uint32_t : 10;
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uint32_t : 10;
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uint32_t condition : 1;
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uint32_t absoluteAddressing : 1;
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ControlFlowOpcode opcode : 4;
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};
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struct ControlFlowCondCallInstruction
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{
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uint32_t address : 13;
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uint32_t isUnconditional : 1;
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uint32_t isPredicated : 1;
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uint32_t : 17;
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uint32_t : 2;
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uint32_t boolAddress : 8;
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uint32_t condition : 1;
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uint32_t absoluteAddressing : 1;
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ControlFlowOpcode opcode : 4;
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};
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struct ControlFlowReturnInstruction
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{
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uint32_t : 32;
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uint32_t : 11;
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uint32_t absoluteAddressing : 1;
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ControlFlowOpcode opcode : 4;
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};
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struct ControlFlowCondJmpInstruction
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{
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uint32_t address : 13;
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uint32_t isUnconditional : 1;
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uint32_t isPredicated : 1;
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uint32_t : 17;
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uint32_t : 1;
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uint32_t direction : 1;
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uint32_t boolAddress : 8;
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uint32_t condition : 1;
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uint32_t absoluteAddressing : 1;
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ControlFlowOpcode opcode : 4;
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};
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struct ControlFlowAllocInstruction
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{
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uint32_t size : 3;
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uint32_t : 29;
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uint32_t : 8;
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uint32_t isUnserialized : 1;
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uint32_t allocType : 2;
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uint32_t : 1;
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ControlFlowOpcode opcode : 4;
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};
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union ControlFlowInstruction
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{
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ControlFlowExecInstruction exec;
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ControlFlowCondExecInstruction condExec;
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ControlFlowCondExecPredInstruction condExecPred;
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ControlFlowLoopStartInstruction loopStart;
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ControlFlowLoopEndInstruction loopEnd;
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ControlFlowCondCallInstruction condCall;
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ControlFlowReturnInstruction ret;
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ControlFlowCondJmpInstruction condJmp;
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ControlFlowAllocInstruction alloc;
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struct
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{
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uint32_t : 32;
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uint32_t : 12;
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ControlFlowOpcode opcode : 4;
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};
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};
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enum class FetchOpcode : uint32_t
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{
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VertexFetch = 0,
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TextureFetch = 1,
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GetTextureBorderColorFrac = 16,
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GetTextureComputedLod = 17,
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GetTextureGradients = 18,
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GetTextureWeights = 19,
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SetTextureLod = 24,
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SetTextureGradientsHorz = 25,
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SetTextureGradientsVert = 26
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};
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enum class FetchDestinationSwizzle : uint32_t
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{
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X = 0,
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Y = 1,
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Z = 2,
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W = 3,
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Zero = 4,
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One = 5,
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Keep = 7
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};
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struct VertexFetchInstruction
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{
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struct
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{
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FetchOpcode opcode : 5;
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uint32_t srcRegister : 6;
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uint32_t srcRegisterAm : 1;
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uint32_t dstRegister : 6;
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uint32_t dstRegisterAam : 1;
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uint32_t mustBeOne : 1;
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uint32_t constIndex : 5;
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uint32_t constIndexSelect : 2;
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uint32_t prefetchCount : 3;
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uint32_t srcSwizzle : 2;
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};
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struct
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{
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uint32_t dstSwizzle : 12;
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uint32_t formatCompAll : 1;
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uint32_t numFormatAll : 1;
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uint32_t signedRfModeAll : 1;
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uint32_t isIndexRounded : 1;
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uint32_t format : 6;
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uint32_t reserved2 : 2;
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int32_t expAdjust : 6;
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uint32_t isMiniFetch : 1;
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uint32_t isPredicated : 1;
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};
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struct
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{
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uint32_t stride : 8;
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int32_t offset : 23;
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uint32_t predicateCondition : 1;
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};
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};
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enum class TextureDimension : uint32_t
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{
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Texture1D,
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Texture2D,
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Texture3D,
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TextureCube
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};
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struct TextureFetchInstruction
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{
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struct
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{
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FetchOpcode opcode : 5;
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uint32_t srcRegister : 6;
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uint32_t srcRegisterAm : 1;
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uint32_t dstRegister : 6;
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uint32_t dstRegisterAm : 1;
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uint32_t fetchValidOnly : 1;
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uint32_t constIndex : 5;
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uint32_t texCoordDenorm : 1;
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uint32_t srcSwizzle : 6;
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};
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struct
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{
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uint32_t dstSwizzle : 12;
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uint32_t magFilter : 2;
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uint32_t minFilter : 2;
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uint32_t mipFilter : 2;
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uint32_t anisoFilter : 3;
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uint32_t arbitraryFilter : 3;
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uint32_t volMagFilter : 2;
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uint32_t volMinFilter : 2;
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uint32_t useCompLod : 1;
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uint32_t useRegLod : 1;
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uint32_t : 1;
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uint32_t isPredicated : 1;
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};
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struct
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{
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uint32_t useRegGradients : 1;
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uint32_t sampleLocation : 1;
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int32_t lodBias : 7;
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uint32_t : 5;
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TextureDimension dimension : 2;
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int32_t offsetX : 5;
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int32_t offsetY : 5;
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int32_t offsetZ : 5;
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uint32_t predCondition : 1;
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};
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};
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union FetchInstruction
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{
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VertexFetchInstruction vertexFetch;
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TextureFetchInstruction textureFetch;
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struct
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{
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FetchOpcode opcode : 5;
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uint32_t : 27;
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uint32_t : 32;
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};
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};
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enum class AluScalarOpcode : uint32_t
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{
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Adds = 0,
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AddsPrev = 1,
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Muls = 2,
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MulsPrev = 3,
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MulsPrev2 = 4,
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Maxs = 5,
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Mins = 6,
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Seqs = 7,
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Sgts = 8,
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Sges = 9,
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Snes = 10,
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Frcs = 11,
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Truncs = 12,
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Floors = 13,
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Exp = 14,
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Logc = 15,
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Log = 16,
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Rcpc = 17,
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Rcpf = 18,
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Rcp = 19,
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Rsqc = 20,
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Rsqf = 21,
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Rsq = 22,
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MaxAs = 23,
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MaxAsf = 24,
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Subs = 25,
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SubsPrev = 26,
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SetpEq = 27,
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SetpNe = 28,
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SetpGt = 29,
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SetpGe = 30,
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SetpInv = 31,
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SetpPop = 32,
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SetpClr = 33,
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SetpRstr = 34,
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KillsEq = 35,
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KillsGt = 36,
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KillsGe = 37,
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KillsNe = 38,
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KillsOne = 39,
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Sqrt = 40,
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Mulsc0 = 42,
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Mulsc1 = 43,
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Addsc0 = 44,
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Addsc1 = 45,
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Subsc0 = 46,
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Subsc1 = 47,
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Sin = 48,
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Cos = 49,
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RetainPrev = 50
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};
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enum class AluVectorOpcode : uint32_t
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{
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Add = 0,
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Mul = 1,
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Max = 2,
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Min = 3,
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Seq = 4,
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Sgt = 5,
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Sge = 6,
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Sne = 7,
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Frc = 8,
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Trunc = 9,
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Floor = 10,
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Mad = 11,
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CndEq = 12,
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CndGe = 13,
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CndGt = 14,
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Dp4 = 15,
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Dp3 = 16,
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Dp2Add = 17,
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Cube = 18,
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Max4 = 19,
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SetpEqPush = 20,
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SetpNePush = 21,
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SetpGtPush = 22,
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SetpGePush = 23,
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KillEq = 24,
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KillGt = 25,
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KillGe = 26,
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KillNe = 27,
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Dst = 28,
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MaxA = 29
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};
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enum class ExportRegister : uint32_t
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{
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VSInterpolator0 = 0,
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VSInterpolator1,
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VSInterpolator2,
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VSInterpolator3,
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VSInterpolator4,
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VSInterpolator5,
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VSInterpolator6,
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VSInterpolator7,
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VSInterpolator8,
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VSInterpolator9,
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VSInterpolator10,
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VSInterpolator11,
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VSInterpolator12,
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VSInterpolator13,
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VSInterpolator14,
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VSInterpolator15,
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VSPosition = 62,
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VSPointSizeEdgeFlagKillVertex = 63,
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PSColor0 = 0,
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PSColor1,
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PSColor2,
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PSColor3,
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PSDepth = 61,
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ExportAddress = 32,
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ExportData0 = 33,
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ExportData1,
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ExportData2,
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ExportData3,
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ExportData4,
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};
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struct AluInstruction
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{
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struct
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{
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uint32_t vectorDest : 6;
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uint32_t vectorDestRelative : 1;
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uint32_t absConstants : 1;
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uint32_t scalarDest : 6;
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uint32_t scalarDestRelative : 1;
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uint32_t exportData : 1;
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uint32_t vectorWriteMask : 4;
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uint32_t scalarWriteMask : 4;
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uint32_t vectorSaturate : 1;
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uint32_t scalarSaturate : 1;
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AluScalarOpcode scalarOpcode : 6;
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};
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struct
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{
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uint32_t src3Swizzle : 8;
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uint32_t src2Swizzle : 8;
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uint32_t src1Swizzle : 8;
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uint32_t src3Negate : 1;
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uint32_t src2Negate : 1;
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uint32_t src1Negate : 1;
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uint32_t predicateCondition : 1;
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uint32_t isPredicated : 1;
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uint32_t constAddressRegisterRelative : 1;
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uint32_t const1Relative : 1;
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uint32_t const0Relative : 1;
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};
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struct
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{
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uint32_t src3Register : 8;
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uint32_t src2Register : 8;
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uint32_t src1Register : 8;
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AluVectorOpcode vectorOpcode : 5;
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uint32_t src3Select : 1;
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uint32_t src2Select : 1;
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uint32_t src1Select : 1;
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};
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}; |